Power depletion and timing intervals of delays are the major parameters as design issues in most efficient VLSI design systems. Most of the digital (VLSI) designs have clock system which consists of distribution network for clock to provide to designs and flip-flops, which consumes most power among all the components. It results in change from 30 percent to 60 percent from the whole system power, whereas 90 percent of power the flip flops are consuming remaining was utilizing by the clock distributing network stage ending divisions which is driving the flip flop. As clock frequency increases, the potential of the flip flop or latch will play an even greater role in the complete cycle time. Different flip flops have been studied with power dissipation calculation of clock gated flip flops has been implemented in this article. In Comparison with the pre-defined flip flops, many drawbacks were observed and have been overcome by using the sense amplifier based flip flops which is an advantageous one among all the edge triggering flip flops.