Traditional adders in digital systems suffer from high propagation delays, power dissipation with limited efficiency which makes the circuits not suitable for high performance applications. Hybrid circuits will minimize the critical path that causes the fastest computations and incorporates low power components that consumes less amount of power when compared to conventional adders. Hybrid adders are adaptable to bit length and can provide maximum bit streams by manipulating the internal logic circuitry. This study focuses on developing a customized and efficient full adder circuit using multiplexers to address issues of delay and power consumption in digital circuit design. In this paper we proposed an efficient design for different adder architectures including Ripple Carry Adder, Carry Look-Ahead Adder, and Carry Skip Adder, and performed detailed parametric analysis which demonstrates the advantages of multiplexer-based adders over conventional adders. The proposed design achieves improved power efficiency and reduced delays compared to conventional gate-based adders. In addition to that, Multiplexer based circuits can provide superior area efficiency with reduced transistor count, and simplified logic implementation which makes them ideal for low-power and high-performance applications in VLSI systems. Overall, this study advances VLSI technology by presenting an innovative approach to full adder design, enhancing power efficiency and performance while paving the way for future low-power design methodologies.